smgen online with Winfy

We have hosted the application smgen in order to run this application in our online workstations with Wine or directly.

Quick description about smgen:

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing.

Audience: Science/Research, Developers, Engineering.
User interface: Command-line.
Programming Language: Perl, VHDL/Verilog.
Categories: